Designing Asynchronous Circuits Using NULL Convention Logic (NCL)Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design techniques, such as wavefront steering and Multi-Threshold CMOS (MTCMOS) for NCL, are discussed. The book culminates with a comprehensive design example of an optimized Greatest Common Divisor circuit. Readers should have prior knowledge of basic logic design concepts, such as Boolean algebra and Karnaugh maps. After studying this book, readers should have a good understanding of the differences between asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power. Table of Contents: Introduction to Asynchronous Logic / Overview of NULL Convention Logic (NCL) / Combinational NCL Circuit Design / Sequential NCL Circuit Design / NCL Throughput Optimization / Low-Power NCL Design / Comprehensive NCL Design Example |
Contents
1 | |
Combinational NCL Circuit Design | 17 |
Sequential NCL Circuit Design | 33 |
NCL Throughput Optimization | 43 |
LowPower NCL Design | 57 |
Comprehensive NCL Design Example | 75 |
Biography | 85 |
Other editions - View all
Designing Asynchronous Circuits using NULL Convention Logic (NCL) Scott Smith,Jia Di Limited preview - 2022 |
Designing Asynchronous Circuits using NULL Convention Logic (NCL) Scott Smith,Jia Di Limited preview - 2009 |
Designing Asynchronous Circuits using NULL Convention Logic (NCL) Scott Smith,Jia Di No preview available - 2009 |
Common terms and phrases
AeqB algorithm architecture asserted Asynchronous Circuits bit-wise completion Boolean circuits Boolean Function C-elements circuitry clock CMOS combinational circuit combinational logic completion signal Completion Sleep Sleep DATA and NULL DATA/NULL cycle DATA0 DATA1 datapath Dcomb deasserted delay-insensitive Digital Circuit dual-rail Early Completion component Early Completion Sleep EC DI Register EC Early Completion embedded registration feedback Figure first flows full adder gate delays hold0 hold1 Inc0 input-complete with respect inverter K-map Karnaugh maps leakage max_delayFW max_outputs Mealy machine minimal modified Moore machines MTCMOS MTNCL Logic EC NCL circuits NCL gate NCL implementation NCL systems NULL wavefront num_stages operands optimized output register product term PSpice quad-rail quad-rail signal rails Register reset requires reset I1 reset to NULL Select Reg semi-static shown in Fig sleep mode static TH22 gate threshold gate throughput transition utilize wavefront steering worse-case XOR function Ydat