Design Automation of Real-Life Asynchronous Devices and Systems, Volume 2The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks is becoming impossible. In static timing analysis process variations and signal integrity issues stretch the timing margins to the point where they become too conservative and result in significant overdesign. Importance and difficulty of such problems push some developers to once again turn to asynchronous alternatives. However, the electronics industry for the most part is still reluctant to adopt asynchronous design (with a few notable exceptions) due to a common belief that we still lack a commercial-quality Electronic Design Automation tools (similar to the synchronous RTL-to-GDSII flow) for asynchronous circuits. The purpose of this paper is to counteract this view by presenting design flows that can tackle large designs without significant changes with respect to synchronous design flow. We are limiting ourselves to four design flows that we believe to be closest to this goal. We start from the Tangram flow, because it is the most commercially proven and it is one of the oldest from a methodological point of view. The other three flows (Null Convention Logic, de-synchronization, and gate-level pipelining) could be considered together as asynchronous re-implementations of synchronous (RTL- or gate-level) specifications. The main common idea is substituting the global clocks by local synchronizations. Their most important aspect is to open the possibility to implement large legacy synchronous designs in an almost "push button" manner, where all asynchronous machinery is hidden, so that synchronous RTL designers do not need to be re-educated. These three flows offer a trade-off from very low overhead, almost synchronous implementations, to very high performance, extremely robust dual-rail pipelines. |
Contents
Introduction | 1 |
Handshake Technology | 19 |
Synchronoustoasynchronous RTL Flow | 43 |
Simple Mutation Circuit | 63 |
Automated Gate Level Pipelining Weaver | 85 |
Applications and Success Stories | 107 |
Common terms and phrases
A+ B+ Advanced Research approach asyn asynchronous circuits asynchronous controllers asynchronous design asynchronous implementation behavior C-element channel Circuits and Systems clock clock signal combinational logic completion detectors concurrency cycle data token datapath de-synchronization delay-insensitive Design Automation design language dual-rail dynamic logic Electronic Design Automation encoding fine-grain pipelined flip–flops function GTL implementations handshake circuits handshake components handshake protocol Haste HB HB HB HB stage input International Symposium Kondratyev latches logic synthesis loops mapping marked graph matched delays micropipeline library Muller pipeline NCL circuits NCL gate NCL system netlist Null operation optimization output performance Petri nets pipeline stages Proc registers Research in Asynchronous RTL synthesis SADT sequential shown in Figure signal simulation single-rail slack matching specification static timing analysis Symposium on Advanced synthesis tools Technology design flow testing tion transitions TSMC Verilog VHDL voltage wires