Logically Determined Design: Clockless System Design with NULL Convention LogicThis seminal book presents a new logically determined design methodology for designing clockless circuit systems. The book presents the foundations, architectures and methodologies to implement such systems. Based on logical relationships, it concentrates on digital circuit system complexity and productivity to allow for more reliable, faster and cheaper products. * Transcends shortcomings of Boolean logic. * Presents theoritical foundations, architecture and analysis of clockless (asynchronous) circuit design. * Contains examples and exercises making it ideal for those studying the area. |
Contents
| xvi | |
| 1 | |
| 13 | |
3 The Structure of Logically Determined Systems | 31 |
4 2NCL Combinational Expression | 59 |
5 Cycle Granularity | 95 |
6 Memory Elements | 113 |
7 State Machines | 131 |
11 Pipeline Buffering | 191 |
12 Ring Behavior | 205 |
13 Interacting Pipeline Structures | 221 |
14 Complex Pipeline Structures | 245 |
Appendix A Logically Determined Wavefront Flow | 271 |
Appendix B Playing with 2NCL | 279 |
Appendix C Pipeline Simulation | 283 |
| 285 | |
Other editions - View all
Logically Determined Design: Clockless System Design with NULL Convention Logic Karl M. Fant No preview available - 2005 |
Common terms and phrases
24 cycle 2D pipelined 2NCL combinational expression 2NCL expression 3NCL 4NCL acknowledge path acknowledge signal binary Boolean functions Boolean logic bubble population bubble shadow bubbles flowing buffer cycles C-element completeness criterion configuration control value control variable cycle 24 cycle period DATA bubble data path DATA value DATA wavefront NULL detect digit encoding fan-in fan-out force zeros full adder function map implemented initialized input–output cycles logic expression Logically Determined Design logically determined system lower pipeline minterm MUTEX N T F NPN classes NULL bubble NULL wavefront optimal orphan paths pipeline structure population period register file registration stage rejoin period renewal path request shadow coverage shadows projected shared completeness path shown in Figure simulation slow cycle slowest cycle steered synchronized Theseus Logic throughput tics upper pipeline value variable WAVE 2 WAVE wavefront DATA wavefront wavefront flows wavefront NULL wavefront wavefront population wavefront propagation wavefronts per 100 XOR XOR XOR