See MIPS RunSee MIPS Run, Second Edition, is not only a thorough update of the first edition, it is also a marriage of the best-known RISC architecture--MIPS--with the best-known open-source OS--Linux. The first part of the book begins with MIPS design principles and then describes the MIPS instruction set and programmers’ resources. It uses the MIPS32 standard as a baseline (the 1st edition used the R3000) from which to compare all other versions of the architecture and assumes that MIPS64 is the main option. The second part is a significant change from the first edition. It provides concrete examples of operating system low level code, by using Linux as the example operating system. It describes how Linux is built on the foundations the MIPS hardware provides and summarizes the Linux application environment, describing the libraries, kernel device-drivers and CPU-specific code. It then digs deep into application code and library support, protection and memory management, interrupts in the Linux kernel and multiprocessor Linux. Sweetman has revised his best-selling MIPS bible for MIPS programmers, embedded systems designers, developers and programmers, who need an in-depth understanding of the MIPS architecture and specific guidance for writing software for MIPS-based systems, which are increasingly Linux-based.
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From inside the book
Results 1-5 of 48
... cache MEM from D-cache RD fromregister file WB toregister file ALU IF MEM FIGURE 1.2 MIPS five-stage pipeline. 1.2 fetch data from the cache; a cache miss is a relatively rare event and we can just stop the CPU when it happens (though ...
... cache (D-cache). On average, about three out of four instructions do nothing in this stage, but allocating the stage for each instruction ensures that you never get two instructions wanting the data cache at the same time. (It's the ...
... caches and performance tuning) were running at 200–250 MHz and keeping SGI in touch with the RISC performance leaders. QED: Fast. MIPS. Processors. for. Embedded ... d applied R4000 chips to 1.4 Great MIPS Chips of the Past and Present 13.
... D). Notes. 1987 MIPS R2000-16 MIPS I External: 4 K+4 K to 32 K+32 K External (R2010) FPU. 1990 IDT R3051-20 4 K+1 K The first embedded MIPS CPU with on-chip cache and progenitor of a family of pin-compatible parts. 1991 MIPS R4000-100 ...
... d get if you were writing a user program for a workstation but chose to look at your code at the assembly level ... cache manipulation, and memory management. But at least we can cut the task into smaller pieces. CPUs are often much more ...
Contents
1 | |
29 | |
53 | |
79 | |
Chapter 5 Exceptions Interrupts and Initialization | 105 |
Chapter 6 Lowlevel Memory Management and the TLB | 131 |
Chapter 7 FloatingPoint Support | 151 |
Chapter 8 Complete Guide to the MIPS Instruction Set | 183 |
Chapter 13 GNULinux from Eight Miles High | 363 |
Chapter 14 How Hardware and SoftwareWork Together | 371 |
Chapter 15 MIPS Specific Issues in the Linux Kernel | 399 |
Chapter 16 Linux Application Code PIC and Libraries | 409 |
Appendix A MIPS Multithreading | 415 |
Appendix B Other Optional Extensions to the MIPS Instruction Set | 425 |
MIPS Glossary | 431 |
References | 477 |
Chapter 9 Reading MIPS Assembly Language | 263 |
Chapter 10 Porting Software to the MIPS Architecture | 279 |
Chapter 11 MIPS Software Standards ABIs | 311 |
Chapter 12 Debugging MIPS DesignsDebug and Profiling Features | 339 |
Online Resources | 478 |
Index | 481 |
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Technische Informatik: eine einführende Darstellung Bernd Becker,Paul Molitor No preview available - 2008 |