See MIPS RunSee MIPS Run, Second Edition, is not only a thorough update of the first edition, it is also a marriage of the best-known RISC architecture--MIPS--with the best-known open-source OS--Linux. The first part of the book begins with MIPS design principles and then describes the MIPS instruction set and programmers’ resources. It uses the MIPS32 standard as a baseline (the 1st edition used the R3000) from which to compare all other versions of the architecture and assumes that MIPS64 is the main option. The second part is a significant change from the first edition. It provides concrete examples of operating system low level code, by using Linux as the example operating system. It describes how Linux is built on the foundations the MIPS hardware provides and summarizes the Linux application environment, describing the libraries, kernel device-drivers and CPU-specific code. It then digs deep into application code and library support, protection and memory management, interrupts in the Linux kernel and multiprocessor Linux. Sweetman has revised his best-selling MIPS bible for MIPS programmers, embedded systems designers, developers and programmers, who need an in-depth understanding of the MIPS architecture and specific guidance for writing software for MIPS-based systems, which are increasingly Linux-based.
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From inside the book
Results 1-5 of 40
... line, and MIPS wanted the R4000 to be selected as DEC's future workstation ... cache or memory. Parity errors are generally fatal (unless there's a known ... cache error exception handler can use base + offset addressing off the zero ...
... cache read to obtain the cache line to be written. 7 DBE 8 Syscall Executed a syscall instruction. 9 Bp Executed a break instruction, used by debuggers. 10 RI Instruction code not recognized (or not legal). 11 CpU Tried to run a ...
... cache L1 D-cache IS IL IA DS DL DA Config1 M MMUSize C2 MD PC WR CA EP FP 31 30 28 27 24 23 20 19 16 15 12 11 8 7 4 ... line size is 2 × 2L bytes. A Associativity—this cache is (A + 1)-way set-associative. So if (IS, IL, IA) is (2, 4, 3) ...
... cache instruction altering cache line => fetch, load, or store in affected line Change to watchpoint register => fetch, load, or store that matches Change of shadow register setting => any use of GPR (an execution hazard) CP0 register ...
... cache and D-cache, respectively) so that an instruction can be read and a load or store done simultaneously. Cached ... line inside the cache store contains one or more words of data and a cache tag field, which records the memory ...
Contents
1 | |
29 | |
53 | |
79 | |
Chapter 5 Exceptions Interrupts and Initialization | 105 |
Chapter 6 Lowlevel Memory Management and the TLB | 131 |
Chapter 7 FloatingPoint Support | 151 |
Chapter 8 Complete Guide to the MIPS Instruction Set | 183 |
Chapter 13 GNULinux from Eight Miles High | 363 |
Chapter 14 How Hardware and SoftwareWork Together | 371 |
Chapter 15 MIPS Specific Issues in the Linux Kernel | 399 |
Chapter 16 Linux Application Code PIC and Libraries | 409 |
Appendix A MIPS Multithreading | 415 |
Appendix B Other Optional Extensions to the MIPS Instruction Set | 425 |
MIPS Glossary | 431 |
References | 477 |
Chapter 9 Reading MIPS Assembly Language | 263 |
Chapter 10 Porting Software to the MIPS Architecture | 279 |
Chapter 11 MIPS Software Standards ABIs | 311 |
Chapter 12 Debugging MIPS DesignsDebug and Profiling Features | 339 |
Online Resources | 478 |
Index | 481 |
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References to this book
Technische Informatik: eine einführende Darstellung Bernd Becker,Paul Molitor No preview available - 2008 |