See MIPS RunSee MIPS Run, Second Edition, is not only a thorough update of the first edition, it is also a marriage of the best-known RISC architecture--MIPS--with the best-known open-source OS--Linux. The first part of the book begins with MIPS design principles and then describes the MIPS instruction set and programmers’ resources. It uses the MIPS32 standard as a baseline (the 1st edition used the R3000) from which to compare all other versions of the architecture and assumes that MIPS64 is the main option. The second part is a significant change from the first edition. It provides concrete examples of operating system low level code, by using Linux as the example operating system. It describes how Linux is built on the foundations the MIPS hardware provides and summarizes the Linux application environment, describing the libraries, kernel device-drivers and CPU-specific code. It then digs deep into application code and library support, protection and memory management, interrupts in the Linux kernel and multiprocessor Linux. Sweetman has revised his best-selling MIPS bible for MIPS programmers, embedded systems designers, developers and programmers, who need an in-depth understanding of the MIPS architecture and specific guidance for writing software for MIPS-based systems, which are increasingly Linux-based.
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From inside the book
Results 1-5 of 93
... result, the pace of architecture development has increased to address the unique needs of these markets: high-performance computation, code compression, geometry processing for graphics, security, signal processing, and multithreading ...
... result of this orientation is that we'll tend to be rather informal when describing things that may not be familiar to a software engineer—particularly the inner workings of the CPU—but we'll get much more terse and technical when we're ...
... result is that, so long as it keeps hitting the cache, the CPU starts an instruction every clock cycle. Let's look at Figure 1.2 and consider what happens in. 1.2 The MIPS Five-Stage Pipeline 5 1.2 The MIPS Five-Stage Pipeline.
... results. At 1986 speeds, this division of function was ingenious, practical, and workable; importantly, it held the number of signal connections on each device within the pin count limitations of the pin-grid array packages commonly ...
... result that the device was never brought to market. After this brief excursion into PowerPC territory, QED resumed its exclusive focus on the MIPS architecture. QED's RM5200 and RM7000 Processors QED's first “own-brand” CPU was the ...
Contents
1 | |
29 | |
53 | |
79 | |
Chapter 5 Exceptions Interrupts and Initialization | 105 |
Chapter 6 Lowlevel Memory Management and the TLB | 131 |
Chapter 7 FloatingPoint Support | 151 |
Chapter 8 Complete Guide to the MIPS Instruction Set | 183 |
Chapter 13 GNULinux from Eight Miles High | 363 |
Chapter 14 How Hardware and SoftwareWork Together | 371 |
Chapter 15 MIPS Specific Issues in the Linux Kernel | 399 |
Chapter 16 Linux Application Code PIC and Libraries | 409 |
Appendix A MIPS Multithreading | 415 |
Appendix B Other Optional Extensions to the MIPS Instruction Set | 425 |
MIPS Glossary | 431 |
References | 477 |
Chapter 9 Reading MIPS Assembly Language | 263 |
Chapter 10 Porting Software to the MIPS Architecture | 279 |
Chapter 11 MIPS Software Standards ABIs | 311 |
Chapter 12 Debugging MIPS DesignsDebug and Profiling Features | 339 |
Online Resources | 478 |
Index | 481 |
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References to this book
Technische Informatik: eine einführende Darstellung Bernd Becker,Paul Molitor No preview available - 2008 |