Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and DesignBehzad Razavi Featuring an extensive 40 page tutorial introduction, this carefully compiled anthology of 65 of the most important papers on phase-locked loops and clock recovery circuits brings you comprehensive coverage of the field-all in one self-contained volume. You'll gain an understanding of the analysis, design, simulation, and implementation of phase-locked loops and clock recovery circuits in CMOS and bipolar technologies along with valuable insights into the issues and trade-offs associated with phase locked systems for high speed, low power, and low noise. |
Contents
BASIC THEORY | 41 |
ChargePump PhaseLocked Loops 1172 | 77 |
Analyze PLLs with Discrete Time Modeling | 94 |
Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery | 107 |
Optimization of PhaseLocked Loop Performance in Data Recovery Systems | 129 |
Noise Properties of PLL Systems | 142 |
Practical Approach Augurs PLL Noise in RF Synthesizers | 155 |
A Simple Model of Feedback Oscillator Noise Spectrum | 180 |
A 6GHz 60mW BiCMOS PhaseLocked Loop with 2V Supply | 325 |
A Variable Delay Line PLL for CPUCoprocessor Synchronization | 333 |
A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors | 339 |
A WideBandwidth LowVoltage PLL for PowerPC Microprocessors | 347 |
A 30128 MHz Frequency Synthesizer Standard Cell | 355 |
CellBased Fully Integrated CMOS Frequency Synthesizers | 361 |
FullyIntegrated CMOS PhaseLocked Loop with 15 to 240 MHz Locking Range and 50 psec Jitter | 369 |
PLL Design for a 500 MBs Interface | 377 |
Analysis Modeling and Simulation of Phase Noise in Monolithic VoltageControlled Oscillators | 195 |
BUILDING BLOCKS | 199 |
MOS Oscillators with MultiDecade Tuning Range and Gigahertz Maximum Speed | 211 |
A Bipolar 1 GHz MultiDecade Monolithic VariableFrequency Oscillator | 219 |
GaAs Monolithic PhaseFrequency Discriminator | 229 |
A PhaseLocked Loop with Digital Frequency Comparator for Timing Signal Recovery | 237 |
A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gbs | 244 |
MODELING AND SIMULATION | 253 |
The Macro Modeling of PhaseLocked Loops for the SPICE Simulator | 259 |
MixedMode Simulation of PhaseLocked Loops | 270 |
Behavioral Simulation Techniques for PhaseDelayLocked Systems | 278 |
A Monolithic PhaseLocked Loop with Detection Processor | 285 |
A 200MHz CMOS PhaseLocked Loop with Dual Phase Detectors | 292 |
HighFrequency PhaseLocked Loops in Monolithic Bipolar Technology | 301 |
A 6GHz Integrated PhaseLocked Loop Using AlGaAsGaAs Heterojunction Bipolar Transistors | 310 |
An Analog PLLBased Clock and Data Recovery Circuit with High Input Jitter Tolerance | 383 |
A 30MHz Hybrid AnalogDigital Clock Recovery Circuit in 2um CMOS | 389 |
A BiCMOS PLLBased Data Separator Circuit with High Stability and Accuracy | 399 |
A Versatile Clock Recovery Architecture and Monolithic Implementation | 405 |
A 155MHz Clock Recovery Delay and PhaseLocked Loop | 421 |
A Monolithic 156 Mbs Clock and Data Recovery PLL Circuit using the SampleandHold Technique | 431 |
A Monolithic 480 Mbs Parallel AGCDecisionClock Recovery Circuit in 1 2µm CMOS | 437 |
A Monolithic 622 Mbsec Clock Extraction and Data Retiming Circuit | 444 |
A Monolithic 2 3Gbs 100mW Clock and Data Recovery Circuit in Silicon Bipolar Technology | 450 |
NMOS ICs for Clock and Data Regeneration in GigabitperSecond OpticalFiber Receivers | 461 |
A PLLBased 2 5Gbs Clock and Data Regenerator IC | 473 |
| 481 | |
| 489 | |
EDITORS BIOGRAPHY | 498 |
Common terms and phrases
acquisition amplifier amplitude analog analysis approximately bandwidth behavior bipolar block diagram capacitance capacitor center frequency characteristic charge pump chip clock and data clock recovery clock recovery circuit CMOS components control voltage cycle data transition delay device differential equation feedback Figure frequency detector frequency difference Gb/s IEEE implemented input data input signal integrated ISSCC jitter latch limit linear lock loop bandwidth loop filter low-pass low-pass filter measured modulation monolithic multiplier nonlinear offset operation parameters performance phase detector phase difference phase error phase jitter phase noise phase-locked loop PLL's pole pull-in range pulse quadricorrelator quency random recovered clock recovery circuit reference regenerator resistor ring oscillator sampling shown in Fig simulation Solid-State Circuits spectrum stage static phase switching sync synchronization Tech tion transfer function transistor VCO frequency voltage-controlled voltage-controlled oscillator waveform zero