VLSI 91: Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration, Edinburgh, Scotland, 20-22 August 1991Arne Halaas, Peter B. Denyer The major problem in VLSI is really the control of complexity. The hardest part is the control of autonomous yet interacting processes. We do not yet have satisfactory techniques for handling that sort of thing, but I think the techniques we need to develop are independent of whether you are programming or designing the chip. Sidney Michaelson, Initiator of the IFIP Working Group on VLSI. This proceedings, dedicated to the late Prof. Sidney Michaelson, who ten years ago established this IFIP Working Group, reflects the continuing interest in improving design tools and the wide range of engineering concerns surrounding the effective exploitation of VLSI. |
Contents
Arithmetic | 1 |
Digital Signal Processing | 19 |
Pipelined BITSerial SYNthesis of Digital Filtering Algorithms | 39 |
Copyright | |
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adder algorithm application architecture asynchronous circuits bit-serial block cell channel chip clock CMOS column combinational logic components computation Computer-Aided Design connected constraints cycle defined delay described Design Automation Conference example fanout finite state machine flip-flop formal function global graph Halaas and P.B. hardware IDCT IEEE IFIP implementation input integrated interconnection interface internal latches layer layout method methodology minimal module multiplexers multiplexor multiplier neuron node operation optimization output P.B. Denyer Eds parallel path performance permutation placement problem Proc processing elements processor array Publishers B.V. North-Holland retiming routing Science Publishers B.V. segments sequential circuit shown in Figure signal simulation solution specification step structure synchronous synthesis systolic array techniques transformations transistor transition relation variables vector vector processor verification VHDL VLSI VLSI 91 wave pipelined wiring workspace