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Digital Signal Processing
Pipelined BITSerial SYNthesis of Digital Filtering Algorithms
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adder algorithm application architecture asynchronous circuits bit-serial block cell channel chip clock CMOS column combinational logic components computation Computer-Aided Design connected constraints cycle defined delay described Design Automation Conference example fanout finite state machine flip-flop formal function global graph Halaas and P.B. hardware IDCT IEEE IFIP implementation input integrated interconnection interface internal latches layer layout memory method methodology minimal module multiplexers multiplexor multiplier neuron node operation optimization output P.B. Denyer Eds parallel path performance permutation petals placement problem Proc processing elements processor array Publishers B.V. North-Holland redundant registers represent retiming Science Publishers B.V. segments sequential circuit shown in Figure signal simulation solution specification step structure synchronous synthesis systolic array techniques transformations transistor transition relation variables vector vector processor verification VHDL VLSI VLSI 91 wave pipelined wiring workspace